1.
Poduel B, Kansakar P, Chhetri SR, Joshi SR. Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL. Nepal Journal of Science and Technology [Internet]. 2015 Feb. 3 [cited 2024 Nov. 21];15(1):81-8. Available from: https://nepjol.info./index.php/NJST/article/view/12021